1. Field of the Invention
The present invention relates to a semiconductor device comprising a memory cell array in which structures of bit lines and sense amplifiers are hierarchized.
2. Description of Related Art
In recent years, semiconductor devices such as DRAM have increased in capacity and decreased in size, and with this, memory cell arrays in which both structures of bit lines and sense amplifiers are hierarchized have been proposed. In such memory cell arrays, there are arranged local bit lines of a lower hierarchy and global bit lines of an upper hierarchy, and there are provided local sense amplifiers connected to the local bit lines and global sense amplifiers connected to the global bit lines. A configuration is known in which hierarchical bit lines of open bit line structure are used in a hierarchical memory cell array (for example, see Patent Reference 1). In this configuration, a differential type local sense amplifier needs to be connected to a pair of bit lines of the open bit line structure. Further, a configuration is known in which hierarchical bit lines of single-ended configuration are used in a hierarchical memory cell array (for example, see Patent Reference 2). In this configuration, a single-ended local sense amplifier needs to be connected to one single-ended bit line.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2011-034614 (U.S. Pat. No. 8,248,834)    [Patent Reference 2] Japanese Patent Application Laid-open No. 2010-055729 (U.S. Pat. No. 8,068,369)
In the above hierarchical memory cell arrays, it is desirable to employ differential type sense amplifiers in order to obtain a sufficient sensing margin when amplifying a minute signal voltage read out from a memory cell. Meanwhile, in consideration of restriction of manufacturing process, the global bit lines formed in a wiring layer over the local bit lines are desired to have a single-ended configuration that is capable of widening a line pitch. However, a memory cell array in which the differential type local sense amplifier is connected to local bit lines of the open bit line structure and a single-ended global sense amplifier is connected to a global bit line of the single-ended configuration has not been proposed. In the memory cell array having such a configuration, a control method of hierarchical switches each of which controls an electrical connection between a pair of local bit lines of the open bit line structure and the single-ended global bit line has not been proposed. As descried above, in the conventional hierarchical memory cell arrays, it is difficult to achieve a configuration that has both advantages of using the differential type sense amplifier and the single-ended global bit line.